ASIC Images Gallery

Name: miniVIPIC Designer: G. Deptuch, F. Fahim, J. Hoff
Process: TSMC CMOS 40nm Experiment: VIPIC
Fabrication Date: 2014 Size: 4.8mm by 5.4mm

Click to enlarge The C8P1 algorithm for the allocation of a hit to a single pixel in the presence of charge sharing in a highly segmented pixel detector was presented. The key elements of the algorithm were described as was the method of implementation. A thorough analysis of the performance of the algorithm was presented through two examples of photon impacts. The miniVIPIC prototype was designed in a 130 nm process as a proof of feasibility of the hardware implementation of the C8P1 algorithm.

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Name: MAMBO III Designer: F. Khalid (Fahim)
Process: T-Micro 3D Integration Experiment: SOIPIX
Fabrication Date: Feb 2010 Size: 5mm by 5mm

Click to enlarge Monolithic Active Matrix with Binary Counters (MAMBO) III 3D ASIC has been designed for detecting and measuring low energy X-rays from 6-12keV. The top ASIC consists of a matrix of 4444 pixels, each of 100x100m2. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC2 shaper and a baseline restorer. It also contains a window comparator with Upper and Lower thresholds which can be individually trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit counter which is reconfigured as a shift register to serially output the data from the entire ASIC.

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Name: NOVA1 Designer: T. Zimmerman
Process: TSMC 0.25µ CMOS Experiment: NOVA
Fabrication Date: Feb 2006 Size: 2.66mm by 5.65mm

Click to enlarge The first prototype of the NOvA is a 32 channel APD readout chip, optimized for APD capacitance of about 10 pF. Input signals are integrated and shaped, with programmable gain and shaping time (several hundred ns). Two readout modes are available. In analog mode, the shaper output (in groups of 8 channels) are serially multiplexed to a common bus, and converted to a differential analog output to directly drive an external ADC. In digital mode, the shaper outputs are sampled by an analog pipeline and digitized by an on-chip 10-bit ADC.

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Name: FRICO Designer: A. Mekkaoui
Process: AMS 0.35µ CMOS Experiment: SNAP
Fabrication Date: June 2006 Size: 4.816mm by 4.430mm

Click to enlarge The FRIC0 ASIC is a test device that implements circuitry in an AMS 0.35 micron CMOS process for providing a large number of bias voltages and currents needed by an infrared sensor device that is a candidate for the Supernova/Acceleration Probe (SNAP) space telescope. The challenge of this device is to meet stringent stability requirements at cryogenic temperatures.

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Name: Digital Calorimeter Chip(DCAL) Designer: A. Mekkaoui, J. Hoff
Process: TSMC 0.25µ CMOS Experiment: International Linear Collider
Fabrication Date: March 2005 Size: 5.25mm by 3.6mm

Click to enlarge The DCAL is a full-custom chip for Digital Calorimetry. Like traditional calorimetry, digital calorimetry attempts to measure the energy of incident particles. However, digital calorimetry uses particle flow algorithms in a 3-dimensional grid of sensors provide simple hit/no-hit information. The energy is determined by a summation of the number of hit sensors.

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Name: Trigger Pipeline + Timing(TRIP_T) Designer: A. Mekkaoui
Process: TSMC 0.25µ CMOS Experiment: D0
Fabrication Date: 2005 Size: 4.8 mm x 4.6 mm

Click to enlarge The TRIP_T is similar to the TRIP chip except that it incorporates circuitry that gives timing information on when a hit occurred. The chip required a major design and layout change to the TRIP chip.

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Name: Resonant Mode Converter Chip(RMCC) Designer: A. Mekkaoui, J. Hoff, A. Boubekeur
Process: AMI 0.5µ CMOS(5 volt process) Experiment: Physics experiments requiring high
Fabrication Date: August 2004 voltage @ low low current
Size: 3.806 mm x 3.403 mm

Click to enlarge The RMCC provides control and monitoring of Cockcroft-Walton high voltage generator circuits by integrating references, DACs, ADCs, and driver circuits in one package. Typical applications are 1-2 KV @ 10 µa.

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Name: Charge Integrator and Encoder -ver 9(QIE9) Designer: T. Zimmerman, J. Hoff
Process: AMS 0.8µ BiCMOS Experiment: BTEV
Fabrication Date: December 2004 Size: 2.620 mm x 4.012 mm

Click to enlarge The QIE9 uses an 8 way current splitter and an 8 bit linear ADC to digitize PMT signals over a 16 bit dynamic range for the BTEV experiment. The device operates at a frequency up to 8 MHz.

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Name: Fermilab Silicon Strip Readout chip -ver 1 Designer: A. Mekkaoui, J. Hoff, V. Re
(FSSR1) Experiment: BTEV
Process: TSMC 0.25µ CMOS Size: 7.27mm by 4.46mm
Fabrication Date: 2004

Click to enlarge The FSSR is a 128 channel readout chip, designed to readout hit data for the BTEV experiment. The control and readout architecture of the FSSR is the same as that for the FPIX2 chip. The chip is intended to operate with beam crossing intervals of 132 to 396 nsec.

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Name: Silicon Vertex Detector Readout - version 4 Designer: Tom Zimmerman, J. Hoff, LBNL
(SVX4) Experiment: Designed for CDF and D0,
Process: TSMC 0.25µ CMOS but only used in D0
Fabrication Date: May 2003 Size: 9.0 mm x 6.257 mm

Click to enlarge The SVX4 is an upgrade of the SVX2 and SVX3 such that the chip can be used in both CDF and DO and run with beam crossings ranging from 132ns to 396 ns. The chip is also designed in a deep submicron process so that it will survive more than 10 Mrads of radiation.

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Name: Channel Control ASIC(CCA) Designer: Ahmed Boubekeur
Process: Agilent 0.5µ CMOS Experiment: CMS
Fabrication Date: February 2002 size: 3.4 mm x 4.0 mm

Click to enlarge The Channel Control ASIC is an interface chip used with the QIE8 for the CMS experiment at CERN. The CCA performs many functions including: synchronization of data from two QIE chips, phased clock generation for the QIEs, programmable test pulses, transmitting known test patterns and error messages to the DAQ.

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Name: Charge Integrator and Encoder -ver 8(QIE8) Designer: T. Zimmerman, J. Hoff
Process: AMS 0.8µ BiCMOS Experiment: CMS
Fabrication Date: June 2002 Size: 3.07 mm x 4.35 mm

Click to enlarge The QIE8 is a charge integrating modified floating point ADC. It has a 4 way current splitter which has ranges that are not binary weighted. The range information is encoded as a 2 bit mantissa. An analog signal is fed to an on chip non linear ADC. The QIE8 is a wide dynamic range device that operates at 40 MHz.

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Name: Trigger Pipeline(TRIP or SIFT) Designer: A. Mekkaoui, J. Hoff, T. Zimmerman
Process: TSMC 0.25µ CMOS Experiment: D0
Fabrication Date: June 2002 Size: 4.55 mm x 4.8 mm

Click to enlarge The TRIP chip is the front end preamplifier, trigger and pipeline chip for the VLPC based detectors at Dzero (central fiber tracker and central and forward preshowers). 32 channels/chip.

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Name: Fermilab Pixel Readout Chip -rev 2(FPIX2) Designer: A. Mekkaoui, J. Hoff
Process: TSMC 0.25µ CMOS Experiment: BTEV
Fabrication Date: 2002 Size: 8.88mm by 10.1mm

Click to enlarge Several improvements were made to the FPIX1 design including the addition of a 3 bit FADC in every pixel cell. The array is 22 x 128 for 50 x 400 µ pixel cells.

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Name: Monolithic Amorphous Silicon Diode Array Designer:Tom Zimmerman
Readout chip(MASDA-X) Experiment:Flat panel medical X-ray imaging
Process: HP 0.5µ(rad hard) CMOS displays at U. of Michigan Hospitals
Fabrication Date: April 2001 Size: 5.527 mm x 12.267 mm

Click to enlarge The MASDA-X is a 128 channel readout chip intended for peripheral attachment to a Megapixel amorphous silicon active pixel array. The chip accepts a + or - polarity input signal and has an 8 bit programmable charge transfer gain to accommodate a wide variety of input signals. Each channel has a sample and hold with DCS. The chip has a programmable bandwidth time constant from <.5 µs to >5 µs to allow for S/N optimization. The analog outputs are multiplexed either 16:1 or 64:1 to a 16 bit ADC. The chip has very low noise and is pipelined to avoid dead time in the image signal acquisition

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Name: Shower Max Charge Integrator and Encoder Designer: J. Joff, et. al.
(SMQIE) Experiment: CDF
Process: Orbit 1.2µ BiCMOS Size: 6.4 mm x 6.4 mm
Fabrication Date: 1999

Click to enlarge The SMQIE was designed to digitize signals from two shower max detectors in CDF: 1) the Central Electromagnetic Strip, and 2) the Plug Shower Max. The chip has two channels. Each channel has an 8 way current splitter and a 5 bit ADC to provide 13 bits of dynamic range, followed by a Level 1 FIFO and Level 2 storage. It intended to operate at 7.6 MHz. (6.4 mm x 6.4 mm)

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Name: DAC Decoder and Regulator(DDR2) Designer: Alpana Shenai
Process: Honeywell(rad hard) 0.8µ CMOS Experiment: CDF
Fabrication Date: February 1998 Size: 2.8 mm x 2.8 mm

Click to enlarge The DDR2 is a support chip for the SVX3 chip used in the CDF experiment at Fermilab. The DDR2 functions include: generates analog references for calibration inject feature of the SVX3, decodes control signals from DAQ system to the SVX3, regulates the power supply voltages for the SVX3.

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Name: Transceiver(TXM) Designer: A. Shenai
Process: Honeywell 0.8µ(rad hard) CMOS Experiment: CDF
Fabrication Date: March 1998 Size: 2.5 mm x 2.5 mm

Click to enlarge The TXM is a 10 bit differential transceiver intended for radiation hard applications. The chip is intended to transmit bi-directional data and commands for the SVX2 chips at DO and between the FIB and SVX3 Port cards at CDF.

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Name: Fermilab Pixel Readout Chip -rev 1(FPIX1) Designer: A. Mekkaoui, J. Hoff
Process: HP 0.5µ CMOS Experiment: BTEV
Fabrication Date: 1998 Size: 7.3 mm x 9.7 mm

Click to enlarge The FPIX1 is a prototype designed to meet the BTEV experiment specifications. The data from the FPIX1 is intended to be used in the Level 1 trigger. The chip is 18 x 160 and is intended for pixels that are 50 µ x 400 µ. The chip incorporates a 2 bit FADC in every pixel cell. The chip operates in a triggered and non triggered mode.

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Name: Silicon Vertex Detector Readout - ver 3(SVX3) Designer: Tom Zimmerman, LBNL
Process: Honeywell 0.8µ(rad hard) CMOS Experiment: CDF
Fabrication Date: 1998 Size: 11.916 mm x 6.257 mm

Click to enlarge The SVX3 is similar to the SVX2 except that it is designed to operate continuously without any acquisition dead time during digitization and readout Other improvements include such things as a deeper analog pipeline.

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Name: Fermilab Pixel Readout Chip -0(FPIX0) Designer: A. Mekkaoui, J. Hoff
Process: HP 0.8µ CMOS Experiment: Pixel R&D
Fabrication Date: 1997 Size: 6.1 mm x 5.0 mm

Click to enlarge The FPIX0 is a prototype pixel readout device for pixels that are 50 µ x 400 µ. The design is 12 columns by 64 rows with an analog readout. Data driven non triggered readout.

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Name: Silicon Vertex Detector Readout - ver 2(SVX2) Designer: Tom Zimmerman, LBNL
Process: UTMC 1.2µ CMOS Experiment: D0
Fabrication Date: 1996 Size: 6.3 mm x 8.9 mm

Click to enlarge The SVX2 is a 128 channel silicon strip readout chip that is meant to interface with detectors having a pitch of about 50 µ. The chip is designed to run with beam crossings of 396 nsec. The chip has an analog pipeline to provide a delay for a level 1 trigger to be formed. Upon receiving a level 1 trigger, the chip stops acquiring data. The selected data is then digitized, sparsified and readout.

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Name: Charge(Q) Integrator and Encoder -ver b6 Designer: T. Zimmerman, M. Sarraj
(QIE5b6) Experiment: KTEV
Process: Orbit 2.0µ BiCMOS Size: 4.1 mm x 4.5 mm
Fabrication Date: May 1995

Click to enlarge The QIE5b6 is the first in a series of chips designed to receive a charge input from a PMT or similar device and provide a digital output. The chip uses a binary weighted 8-way current splitter for simultaneous signal processing on 8 ranges. The chip encodes the range as a 3-bit mantissa and outputs an integrated analog signal for digitization by an off chip ADC.

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