Full mesh backplane link test results.
|Rear Transition Module 2.0
The Pulsar IIa prototype board is a general purpose processing engine based on a pair of Xilinx Kintex XC7K325T FPGAs. Each FPGA interfaces with two FMC mezzanine cards, DDR3 memory, the ATCA full mesh backplane (9 x 10Gbps), RTM (6 x 10Gbps) and a local interconnect bus (20Gbps). The Pulsar IIa is a successor to the Pulsar VME board widely used at CDF and MAGIC.
Compatible with our FMC Test Mezzanine.
Mini Backplane 1U Chassis
The Mini Backplane is used to power a single
ATCA front board and RTM. This new layout is compatible with a
commercially available 1U chassis (contact us for details). This
chassis is powered from a 48VDC supply and includes up to 9 high
velocity fans and a fan controller board. On the Mini Backplane board
the IPMB signals are brought out to testpoints and the Base Interface (
10/100/1000 Ethernet) Channel 1 is brought out to an RJ45 connector.
All Fabric Channels are looped back to facilitate quick checkout of the
Pulsar II front board transceivers.